In view of the device and interconnect densities required in present day integrated circuits, it is imperative that the manufacturing processes be carried out with utmost precision and in a way that minimizes defects. For reliable operation, the electrical characteristics of the circuits must be kept within carefully controlled limits, which implies a high degree of control over the myriad of operations and fabrication processes. Once defective integrated circuits have been identified, it is desired to take steps to decrease the number of defective integrated circuits produced in the manufacturing process, thus increasing the yield of the integrated circuits meeting specifications.
In the past, many of the defects which caused poor yield in integrated circuits were caused by particulate contaminants or other random sources. Increasingly, many of the defects seen in modern integrated circuit processes are not sourced from particulates or random contaminants, especially in the earlier stages of process development or yield ramping, but rather stem from very systematic sources. Some of these systematic sources can be tied to specific characteristics of an IC design, such as the presence of a large number of metal-filled vias or contacts. Due to the way data bits are programmed in Read Only Memory (ROM), some ROMs contain high numbers of vias and/or contacts, which can have a systematic adverse impact on the yield of the process.
Some systematic yield problems are dealt with after production begins. However, the costs of development and today's compressed timelines make it desirable to analyze a proposed design to predict yield problems before actually producing a final product IC wafer. By identifying characteristics of an IC design that are likely to have unfavorable impact on yield, these design problems can be corrected before a full set of masks is made for the IC.